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Design Engineer Interview Questions
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Static Timing Analysis
What is the input offset voltage for a folded cascode amplifier
Recruiter questions: 1. Why this job? 2. What happens to performance of invertor when body is tied to -ve voltage? 3. How will propagation delay of invertor scaled with sizes of PMOS and NMOS? Director phone screen: 1. MOSFET capacitance variation with gate voltage, list three regions this C. 2. I-V characteristic of NMOS whose drain is tied to Vdd, Source/Body to Gnd and Gate.voltage is sweep from 0 to Vdd. Mention different regions of this curve. 3. How will NMOS drain current scale with temperature variation? 4.Consider a blackbox circuit that sources current 'I'. What tests will you perform on it?
Describe the handshake between UVM agent and UVM sequencer
what were you working at in your previous company ? my experience ? low power questions ?
Explain gray code and FIFO techinique?
Five ways to find if an integer is even or odd in C.
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