A state machine question for complex input signal.
Design Digital Interview Questions
820 design digital interview questions shared by candidates
Have you worked in Canva before? Where do you stay up-to-date on the latest design trends?
How to synchronize with a FIFO.
Effect clock skew on setup /hold time
What was your concept and process behind this project?
what is setup and hold time?
The interviewer asked me some basics questions like frequency divide by 3, D-FF, transform DFT.
How to divide a clock by 3 without using PLL?
Typical verilog questions which you find
3) Flip flop A -> Flip flop B -> Flip flop C - output of Flip flop is C is connected to Flip flop A. Combinational delay between A and B is 3ns, b/w B and C is 4ns, b/w C and A is 5ns. Case a) Find max operating freq? [setup = 1ns, hold = 1ns,clock to q =0] Case b) Now make the flip flop B , neg edge triggered . Find max operating freq?
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