The process took 3 weeks. I interviewed at Qualcomm (San Diego, CA) in Sep 2011
Interview
Applied online via thier career site. Received an email notification after a few days to schedule a phone interview allowing a few days notice so I scheduled it for the following week. The phone interview seemed to focuse on your communication skills as it was just to describe what your responsibilites were and what kind of experience you had. Nothing really to test your techincal skills at all, no scenarios, no quizzes, just your background. You can then ask questions to you interviewer. Phone interview was about 30 - 45 minutes.
If they are still interested in you as a candidate, you get an email to schedule to come in for a group panel interview. Again they request a few days notice for you available windows and again, I scheduled it for the following week. Once notified you will receive an email confirmation for the date and location. During my panel interview, it consisted of the dept manager and a few senior level technicians/analysts. Here they would ask you things based heavily on your resume, how you would handle certain situations, both technical and personal. After the interview you would then see the talent consultant usually in another building to go over the overall experience, benefits and salary. Perhaps a bit premature?
this is where my journey ends as i receive via email that I am not quite the fit they are looking for.
Interview questions [2]
Question 1
What was the most difficult problem you encountered and how did you resolve it?
I applied through college or university. The process took 1 week. I interviewed at Qualcomm in Oct 2011
Interview
Resume was shortlisted and I was called for the interview. 2 rounds of Technical Interview for Design & Verification. Verification Interview was on state machine design, Verilog coding & scheduling problems. Should be easy if you are strong in Digital Eletronics. Design Interview was standard. The interviewer asked me to design an Asynchronous FIFO; False paths, Multi-Cycle paths; Clock Domain Conversion; 1 bit transfer between 2 different clocks; Metastability etc..