I interviewed at Qualcomm (San Diego, CA) in Dec 2012
Interview
Had a phone interview followed by 3 rounds of onsite interview. Few questions on verilog coding, state machine to realize time domain crossing between clock domains, layout practises to minimize diffucion cap/power, leakage paths in SRAM, latchup, effect of temperature on MOS, combinational gate realizations etc..Also some questions on the projects mentioned in the resume.
Interview questions [1]
Question 1
state machine to realize time domain crossing between clock domains