Interview process has 3 rounds , based on each round they will be eliminated people,I went through last round ,and first round basic digital.design question and next round is deep questions on projects worked third is puzzle based
I applied through a recruiter. I interviewed at Qualcomm in Dec 2025
Interview
The interview process for an ASIC Design Verification (DV) Engineer typically includes resume screening, one or more technical phone or online interviews focusing on digital fundamentals, SystemVerilog, UVM, and debugging skills, followed by multiple in-depth technical and behavioral interview rounds assessing verification methodology, problem-solving ability, and teamwork.
Interview questions [1]
Question 1
They mainly asked me to explain how to build and debug a UVM-based verification environment, including the roles of sequences, drivers, monitors, scoreboards, and how I handled a real bug or coverage issue during a project.
I applied online. I interviewed at Qualcomm in Nov 2025
Interview
There were 2 people asking about my background. Then they shared a platform with me to debug a programming problem. I sovled the tasks and debug the code. They seemed to want me for the job but they didn't respond me after the interview.
Interview questions [1]
Question 1
Debugging a programming challenge and background questions