I applied through a recruiter. The process took 2 weeks. I interviewed at NVIDIA (Santa Clara, CA) in Jun 2012
Interview
Reasonable phone screen and then face to face interviews. Interview process was fairly common. Nothing out of the ordinary or unusual. Well handled overall. Interviewers were enthusiastic and genial
I applied through college or university. The process took 2 days. I interviewed at NVIDIA (Vāranāsi) in Dec 2016
Interview
Nvidia came to our campus on 30th Nov for test and Dec 1st for Interview. Hiring process was done in two steps. First round was a descriptive test (1 hr) covering Digital Design, Cache concepts, CMOS properties, fault detection etc. Paper was pretty much easy, but a bit lengthy.
Interview questions [1]
Question 1
Panel was of 3 members and each candidate is interviewed for 40-50 min.
First they asked about area of interest. When I answered Architecture, three of them asked basic questions on Cache, PIC, DMA, Fault Detection etc.. One of them asked if given a chance, which question in the paper would you attempt ? I corrected my mistake in fault detection
I applied through an employee referral. The process took 3 weeks. I interviewed at NVIDIA in Sep 2016
Interview
Three 45 min phone interviews. First was timing analysis intensive and went into a lot of detail about timing fix techniques. I was really really sleep deprived during this interview and we spent 20 min talking about the pros and cons of upgrading metal layers... Not sure how I passed this interview. Second was more comp arch focused but ended in more timing analysis questions, some of which were redundant. Third was with HM, half was just talking about potential roles and answering my questions, other half was about describing projects and some more technical problems, asked more redundant timing analysis questions. They really wanted to make sure I knew backend I guess...
Interview questions [1]
Question 1
Typical timing probs (fix hold time and setup time violations, power saving techniques, jitter, skew)
Some simple comp arch (5 stage pipeline, hazards and how to fix them, VM)
HM asked me to go through my projects in detail and describe logic synthesis on an FPGA, design an arbiter, list all timing fixes I knew and explain in detail.