How long have you been doing design verification? How familiar are you with UVMF?
Verification Engineer Interview Questions
2,559 verification engineer interview questions shared by candidates
Did I have any training institute experience
Break down how you would machine these cad files.
Questions on digital electronics ,verilog
Basic Mux design, C coding, Verilog register-related questions and counter design related questions, and RISC-V related questions.
Some silly leetcode style question.
Design frequency divider by 3 with 66.66 d. c
none, the problem was that they were shooting questions related to completely different things. The questoins weren't even related to each other.
System verilog and c based questions Fork join , assertions , coverage
Surprisingly few technical questions. Verifying a FIFO was the only real one (I think I might have got asked this twice actually). They also didn't actually ask me any coding questions (reverse a list or whatever). So I recommend preparing some presentation-level answers (without slides of course) about former work you've done because you'll be talking about it a lot!
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