FIFO depth, and ASYNC FIFO test plan
Verification Engineer Interview Questions
2,559 verification engineer interview questions shared by candidates
pseudocode for factorial and think of cases that would fail it, they had given me a scenario and to assess it. A design was given and was asked to identify bugs in it.
Prepare a testbench. (Write in Verilog on the board)
digital, sv, uvm, verilog, scripting basics
Questions on pipelining
register vs flip-flop
1. Programming questions like Fibonacci series. 2. Some questions related to Perl Programming. 3. Some questions on state machine design. 4. Synthesizable and non synthesizable constructs in Verilog. 5. Be thorough with the stuff on the resume.
How would you verify a that a basic flip-flop works?
Technical Screening: Q: I was asked about basic programming questions like Leet Code (easy) but mostly based on array, hash-maps, strings and also resume discussion Full-Panel: Q: SystemVerilog constraints, fork-join, mailbox and semaphores based questions Q: Was asked to write scoreboard for a Asynchronous FIFO Q: Monitor and scoreboard code for an AXI write transaction (project based) Q: Resume based discussions Q: Some basic programming problems in language of preference
What is setup and hold time What is skew What is synchronous and asynchronous reset
Viewing 2291 - 2300 interview questions